Implementation of Risc Processor in Fpga Using Verilog Essay

Reduced counseling- exercise set computers (RISC) be designed to have a lilliputian set of operating directions that execute in short clock cycles, with a sm tout ensemble number of cycles per development. RISC gondolas are optimized to achieve efficient pipelining of their training streams. The machine also serves as a starting point for developing architectural variants and a more robust knowledge setDesigners make high-altitude tradeoffs in selecting an architecture that serves an application. Once architecture has been selected, a circuit that has ample surgery (speed) must be synthesized. Hardware description languages (HDLs) play a key role in this process by modeling the trunk and serving as a descriptive medium that can be used by a synthesis tool.2. RISC (Reduced development destiny Computer)The nature of RISC architecture and semiconductors rapid technical improvements, RISC plant platforms have become the best choice for embedded applications.RISC performanc e characteristicsPower CriticalBattery catered and typically little than 2 Watts of power consumption for a whole SBC using an ARM processor, compared to or so 15+ Watts for a x86-based SBC.Space CriticalWith a low power solution, the main system can fit into very compact space, eliminating alter dissipation concerns.Environmental CriticalBecause of the lack of heat generation, the RISC system can be fully enclosed for total protection from the environsCost CriticalRISC embedded solutions usually come with application-oriented processors that render a lower cost of ownership because of faster time to market, less development risk and greater overall added value.Typical RISC applications industrial mobile platforms Touch based Human Machine Interface (HMI) smear of information (POI) or Point of Scales (POS) In vehicle Telemetric Data aggregator Security restraint2.1 STEPS INVOLVED IN THE PROJECT3.3. architecture of RISC Stored Program MachinepicThe machine consists of thr ee functional units processor Controller MemoryProgram instructions and data are stored in repositing. In program-directed operation, instructions are fetched synchronously from retentivity, decoded, and penalize to operate on data within the arithmetic and logic unit (ALU) change the table of circumscribe of storage chronicles change the contents of the program counter (PC), instruction put down (IR) and the call in demo ( match_R) change the contents of storage, Retrieve data and instructions from memory control the movement of data on the system busses.The instruction register contains the instruction that is currently being executed. The program counter contains the promise of the next instruction to be executed and the address register holds the address of the memory location that will be addressed next by a read or write operation3.1 RISC_SPM ProcessorThe processor includes registers, datapaths, control lines, and an ALU capable of performing arithmetic and logic o perations on its operands, subject to the opcode held in the instruction register. A multiplexer Mux_l, determines the witnesser of data for Bus_l, and a irregular mux, Mux_2, determines the consultation of data for Bus_2. The arousal datapaths to Mux_l are from four interior(a) general-purpose registers (RO, Rl, R2, R3), and from the Pc. Thecontents of Bus_l can be steered to the ALU, to memory, or to Bus_2 (via Mux_2). The input datapaths to Mux_2 are from the ALU, Mux_l, and the memory unit. Thus, an instruction can be fetched from memory, placed on Bus_2, and pissed off into the instruction register. A say of data can be fetched from memory, and steered to a general-purpose register or to the operand register (Reg_Y) prior to an operation of the ALU. The core of an ALU operation can be placed on Bus_2, extended into a register, and subsequently transferred to memory. A dedicated register (Reg_Z) holds a sag indicating that the case of an ALU operation is 0.3.2 RISC_SP M ControllerThe timing of all bodily process is determined by the controller. The controller must steer data to the proper coating, according to the instruction being executed. Thus, the design of the controller is strongly dependent on the spec of the machines ALU and datapath resources and the clocking scheme available. Here a iodine clock is used, and execution of an instruction is initiated on a single knock against of the clock (the rising edge). The controller monitors the state of the processing unit and the instruction to be executed and determines the value of the control signals. The controllers input signals are the instruction word and the zero flag from the ALU. The signals produced by the controller are identified as followspicThus the control unit determines when to load registers selects the path of data through the multiplexers determines when data should be written to memory Controls the three-state busses in the architecture.RISC SPM Instruction SetThe machin e is controlled by a machine language program consisting of a set of instructions stored in memory. So, in addition to depending on the machines architecture, the design depends on the processor instruction set (i.e., the instructions that can be executed by a program). A machine language program consists of a stored sequence of 8-bit words (bytes). The format of an instruction of RISC_SPM can be large or short depending upon the operation.Short instructions have the format opcode source destination 0 0 1 0 0 1 1 0 Each shot instruction requires one byte of memory. The word has a 4-bit opcode, a 2-bit source register address, and a 2-bit destination register address.Long instructions have the format opcode source destination 0 1 1 0 1 0 Dont Dont cares cares address 0 0 0 1 1 1 0 1 A long instruction requires 2 bytes of memory. The first word of a long instruction contains a 4-bit opcode. The remaining 4 bits of the word can be used to expres s the address of a pair of source and destination registers, depending on the instruction. The second word contains the address of the memory word that holds an operand required by the instruction. Theinstruction mnemonics and their actions are limited below.Single-Byte Instructions NOP Here no operation is performed all registers retain their values. The address of the source and destination registers is dint cares, they have no effect. ADD Adds the contents of the source and destination registers and stores the expiry into destination register. AND Forms the bitwise-and of the contents of the source and destination registers and stores the result into the destination registers. NOT Forms the bitwise-and of the contents of the source register and stores the result into the destination register. SUB Subtracts the contents of the source register from destination register and stores the result into source register. Two-Byte Instructions RD Fetches a memory word from the location specified by the second byte and loads the result into the destination register. The source register bits are applyt cares which office that they are unused. WR Writes the contents of the source register to the word in memory specified by the address held in the second byte. The destination register bits are dont cares which means that they are unused. BR Branches the practise flow by loading the program counter with the word at the location (address) specified by the second byte of the instruction. The source register bits and the destination register bits are dont cares which means that they are unused. BRZ Branches the activity flow by loading the program counter with the word at the location (address) specified by the second byte of the instruction if zero flag register is asserted. The source register bits and the destination register bits are dont cares which means that they are unused.Instruction set of RISC_SPM machine Instruction Instruction Word Action Opcode S ource Destination NOP 0000 None ADD 0001 src dest dest